![]() ![]() As for PCIExpress, the core is too huge to compile and run at the same time for 32 bit environment, it is recommended to compile and run under 64bit OS environment.You can increaseĪrchive size from default setting of 400MB, for example, to 10GB, but mayīe more preferred to use selective save or VCD from the viewpoint of simulation speed. ![]() A Disk may be easily full because generated netlist are huge.(Required libraries are displayed in MegaWizard.) Add Lib Dir for the folder which has many generated module files.Add generated module in the folder of testbench.The following is an example of project by using SratixⅢ for DDR3 controller. Model " in MegaWizard as well as simple test bench.) ( The gate level models are generated by checking "Generate Simulation You can simulate WegaWizard generated gate-level simulation model. Th sample project is locatedĥ.1.5MegaWizard Generated IP's simulation Simulation by Gate (altera\sram_initialize_HEX\simulation\custom) Simulation by RTL (altera\sram_initialize_HEX) Set HEX file(generated by above operation) as memory initialization Set appropriate bit width and words in MegaWizard. Should be converted to verilog file by altera_mf.v.) (Since Veritak can not read mif file directly, we use HEX file, which Memory pattern is incremental here in example. Memory words = 1024 ,and bit width of word =32bits Af first,make memory initialization file by Using Quartas2. ![]()
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |